About the course
Reconfigurable platforms like FPGA and CPLDs have now become synonymous to high performance electronic systems. Knowledge of these platforms along with Verilog programming language is essential for science, electronics, communication, instrumentation and electrical engineering students. Also computationally intensive applications at places like Stock Exchanges, defense systems are now based on these platforms. Hence computer and IT professionals should also have working knowledge of these tools.
This training will be an intensive 40 hours course that will involve the design and implementation of various aspects of Front End VLSI that will be tested using Field Programmable Gate Arrays. This course will teach the learners simulation and hardware concepts of designing digital circuits. This course will involve mini-project and one main course project.
Pre-requisites
Digital System Design
Industries where this course will be useful
Several hardware design companies and EDA companies like Xilinx, Altera, Broadcom, Intel, Arm, Cadence, Sankalp Semiconductors etc. Many small scale industries in India do FPGA based design.
Course Outcomes
- Ability to design a hardware using Verilog HDL
- Ability to perform physical verification of the designed Hardware on FPGA
- Ability to use various modeling techniques as per the requirement
- Ability to write Test-benches for verification
Course Instructor
Dr. Surendra S. Rathod received Ph.D. from I.I.T. Roorkee. Currently he is working as professor at Sardar Patel Institute of Technology Mumbai. He has 19 years of teaching experience. His special fields of interest include VLSI design, device modeling and circuit simulation. He has guided several UG and PG projects in the domain of VLSI, embedded systems and instrumentation. He is also Ph.D. guide of Mumbai University. He has worked on various platforms of SoC, FPGA, CPLD and microcontrollers. He has proficiency in SPICE, VHDL, Verilog, SystemVerilog, Xilinx ISE, Vivado, CoventorWare, COMSOL and LabVIEW programming.
He received recognition as IUCEE (Indo Universal Collaboration for Engineering Education) faculty fellow in 2016. He is also awarded as distinguished professor & distinguished HOD by CSI in 2017. He also received ISTE Best Engineering Faculty award in 2012.
Mr. Ganesh Gore is currently the Chief Technical Officer (C.T.O) at Eduvance. He has over 8 years of Experience in the field of Electronic Systems Design, Embedded Systems, High Speed System Design, Circuit Board Design, Circuit Simulations and Device Modeling.
He has successfully taken over 50 projects from concept to market with different companies in a variety of domains such as Systems Control, Healthcare, Defense and Education. Ganesh’s most noteworthy project has been the launch of the Eduvance RemoLabs, a first of its kind online embedded systems learning platform. He has been a Research fellow at IIT Bombay where he worked on Circuit Simulations and Device Modeling. He has worked on a variety of technologies and platforms such as PIC, AVR, Bluetooth, GPS, WIFI, FPGA and Software controlled Embedded Systems. He also has various patents filed in his name.
Prof. Pawankumar Fakatkar is currently working as an Assistant Professor in Electronics Engineering Department at Sardar Patel Institute of Technology, Mumbai. He has over 3 years of experience in training and skill development programs. His areas of interest are embedded systems, circuit simulation and VLSI design. Pawankumar is involved in Research related to Social Innovations. He received Techno Inventor award from Indian Electronics and Semiconductor Association for his outstanding contribution for his project in water quality monitoring. He has worked on various platforms like ARM, PIC, AVR, Zynq 7000 SOC, Cypress PSOC and Xilinx FPGA’s. Pawankumar holds a Master’s degree in Electronics and Telecommunication Engineering Bachelor’s degree in electronics engineering from the University of Mumbai.
Course Layout
- Session – 1 : Introduction to FPGA design flow from conceptualization to physical implementation
- Session – 2 : Introduction of FPGA based Designs and Basic Digital Elements.
- Session – 3 : Hardware Description language Introduction to Verilog HDL – Difference between programming language and HDL Fundamentals of Verilog HDL (Behavioral, Dataflow and Structural modeling
- Session – 4 : Implementation of Combinational Circuit design Concepts
- Session – 5 : Interfacing on Board Switches and Seven Segment with FPGA
- Session – 6 : Implementation of Mini Project – Universal Barrel Shifter
- Session – 7 : Design verification Understanding RTL Schematic
- Session – 8 : Concept of Testbench for VLSI designs,Types and Structure of testbenches
- Session – 9 : Writing Linear Testbench and Simulation for verification