Course Resources
Session 1: Introduction to FPGA design flow from conceptualization to physical implementation
- 1.1. Introduction to FPGA.
- https://www.youtube.com/watch?v=Z0LUhRPMmY4
- https://www.youtube.com/watch?v=8POZhFHxBLs
- https://www.youtube.com/watch?v=gUsHwi4M4xE
- 1.2. FPGA Design Flow.
- 1.3. History of HDL
- 1.4 FPGA Application Area’s Overview:
- 1.4.1 FPGA Video Transmission.
- 1.4.2 Face Detection
- 1.4.3 Control XBox 360, 3D Printers
Session 2: Introduction to Verilog Constructs:
- 2.1 Introduction to Verilog.
- 2.2 Verilog Basics.
- 2.3 Verilog Datatypes.
- 2.4 Verilog Operators.
- 2.5 Level of Abstractions.
Session 3: Combinational circuits with Verilog:
- 3.1 Design of Fundamental Logic Gates like AND, OR and NOT gate with Verilog
- 3.2 Design of universal Gate like NAND, NOR with Verilog
- 3.3 Design of Miscellaneous Gates like XOR, XNOR with Verilog
- 3.4 Understanding Dataflow Modeling Style in Verilog
- 3.4.1 Half Adder using Dataflow Modeling Style.
- 3.4.2 Full Adder using Dataflow Modelling Style.
- 3.5 Understanding Behavioral Modeling Style in Verilog
- 3.4.1 Half Adder using Behavioral Modeling Style.
- 3.4.2 Full Adder using Behavioral Modeling Style.
- 3.6 Understanding Structural Modeling Style in Verilog
- 3.4.1 Half Adder using Structural Modeling Style.
- 3.4.2 Full Adder using Structural Modeling Style.
- 3.7 Introduction to Wire and Reg in Verilog.
Session 4: Sequential Circuit Design.
- 4.1 Introduction to Sequential Circuits
- 4.2 D flipflop Implementation in Verilog
- 4.3 D Flipflop Implementation with Basic Gates(Structural Modeling Style)
- 4.4 Design of 8-bit Counter
- 4.5 4 bit Shift Register
- 4.6 Blocking Vs Non Blocking Statements
- 4.7 Moore State Machine
- 4.8 Mealy State Machine
- 4.9 FSM Design in Verilog
- 5.1 Writing Testbench in Verilog
- 5.2 Test bench for Full adder circuit.
- 5.3 Test bench for Shift Register
- 6.1 Implementation of 3 : 8 Decoder on FPGA
Session 5 : Testbench
Session 6: Introduction to FPGA Programming